Title :
An optimizer for hardware synthesis
Author :
Bhasker, J. ; Lee, Huan-Chih
Author_Institution :
AT&T Bell Labs., Allentown, PA, USA
Abstract :
A description is given of a process-graph analyzer, i.e. a program that optimizes an algorithmic hardware description while endeavoring to attain maximum speed with the minimum commitment to resources. The analyzer is part of the V-Synth system. The four major subsystems of the analyzer-the decomposer, the optimizer, the control-state generator, and the translator-are discussed. Because both its input and output are in VHDL, VHDL itself is discussed. Preliminary test results for the analyzer are presented.<>
Keywords :
circuit layout CAD; logic testing; V-Synth system; VHDL; algorithmic hardware description; control-state generator; decomposer; hardware synthesis; optimizer; process-graph analyzer; program; translator; Circuit simulation; Circuit synthesis; Control systems; Costs; Hardware; Logic; Network synthesis; Parallel processing; Program processors; Testing;
Journal_Title :
Design & Test of Computers, IEEE
