Title :
Chip-level modeling with HDLs
Author_Institution :
Dept. of Electr. Eng., Virginia Polytech. Inst., Blacksburg, VA, USA
Abstract :
VLSI circuits have made gate-level modeling of large-scale systems impractical. Chip-level modeling offers an alternative approach to model development that still represents timing accurately. The authors examine this approach to modeling and the use of hardware description languages (HDLs) to achieve the desired accuracy. The characteristics of chip-level models are reviewed and sample models are presented. HDL code for each model is given to illustrate its use. Fault modeling in a chip level is examined.<>
Keywords :
circuit CAD; digital systems; electronic engineering computing; specification languages; VLSI circuits; chip-level models; fault modeling; hardware description languages; large-scale systems; timing; Circuits; Clocks; Delay; Hardware design languages; Logic; Microprocessors; Registers; Silicon; Switches; Timing;
Journal_Title :
Design & Test of Computers, IEEE
