Title :
A 10:4 MUX and 4:10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link
Author :
Ono, Goichi ; Watanabe, Keiki ; Muto, Takashi ; Yamashita, Hiroki ; Fukuda, Koji ; Masuda, Noboru ; Nemoto, Ryo ; Suzuki, Eiichi ; Takemoto, Takashi ; Yuki, Fumio ; Yagyu, Masayoshi ; Toyoda, Hidehiro ; Kono, Masashi ; Kambe, Akihiro ; Umai, Seiichi ; Sai
Author_Institution :
Central Res. Lab., Hitachi, Ltd., Tokyo, Japan
Abstract :
The first CMOS "gearbox LSI" based on 65-nm CMOS technology-namely, a 2-W 100-Gigabit-Ethernet gearbox LSI combining a 10:4 multiplexer and a 4:10 demultiplexer - was developed. Its power dissipation is 75% lower than that of a conventional SiGe-based gearbox LSI. To develop this low-power gearbox LSI, the power dissipation of its 25-Gb/s interface is decreased to 14 mW/Gb/s by three circuit schemes: maximizing the use of CMOS circuits, adopting a low-power circuit architecture for a current-mode-logic (CML) circuit, and minimizing clock distribution by using a flip-flop with a single-clock operation and a PLL with phase rotation for each channel. The 25-Gb/s interface in the LSI provides a transmitter output with sufficient eye opening and achieved minimum input sensitivity of 34.4-mV (peak-to-peak).
Keywords :
CMOS integrated circuits; Ge-Si alloys; current-mode logic; flip-flops; integrated optics; large scale integration; multiplexing equipment; optical fibre LAN; phase locked loops; 100-Gigabit Ethernet link; 4:10 DEMUX gearbox LSI; CMOS gearbox LSI; SiGe; bit rate 25 Gbit/s; clock distribution; current-mode-logic circuit; flip-flop; low-power circuit; phase locked loops; power 2 W; size 65 nm; voltage 34.4 mV; CMOS integrated circuits; Large scale integration; Phase locked loops; Power dissipation; Receivers; Transmitters; 100-Gigabit Ethernet; Clock and data recovery; demultiplexer; gearbox; low power dissipation; multiplexer; phase locked loop; transceiver;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2011.2168869
