• DocumentCode
    1361566
  • Title

    Study of the extended p+ dual source structure for eliminating bipolar induced breakdown in submicron SOI MOSFET´s

  • Author

    Verma, Vikram ; Kumar, M. Jagadesh

  • Author_Institution
    Indian Inst. of Technol., Delhi, India
  • Volume
    47
  • Issue
    8
  • fYear
    2000
  • fDate
    8/1/2000 12:00:00 AM
  • Firstpage
    1678
  • Lastpage
    1680
  • Abstract
    Simulation results on a novel extended p+ dual source SOI MOSFET are reported. It is shown that the presence of the extended p + region on the source side, which can he fabricated using post-low-energy implanting selective epitaxy (PLISE), significantly suppresses the parasitic bipolar transistor action resulting in a large improvement in the breakdown voltage. Our results show that when the length of the extended p+ region is half the channel length, the improvement in breakdown voltage is about 120% when compared to the conventional SOI MOSFET´s
  • Keywords
    MOSFET; semiconductor device breakdown; silicon-on-insulator; PLISE; Si; bipolar induced breakdown elimination; breakdown voltage improvement; extended p+ dual source structure; floating body effect; parasitic bipolar transistor action suppression; post-low-energy implanting selective epitaxy; submicron SOI MOSFET; Aluminum; Bipolar transistors; Electric breakdown; Epitaxial growth; Insulation; MOSFET circuits; Medical simulation; Silicidation; Silicon on insulator technology; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.853048
  • Filename
    853048
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1361566