High-radix digit serial division

A new area-time efficient digit serial division algorithm and its architecture are presented. In existing digit serial algorithms based on 2´s complement number representation, m cycles are required to generate each quotient bit (m is the number of radix-2ⁿ digits of the word, N). In the new algorithm, K quotient bits are generated in m+K-1 cycles instead of mK cycles. Performance comparisons have shown that the new algorithm is up to K times faster and moreover for small values of K it requires a smaller area than existing digit serial algorithms that are based on 2´s complement number representation. More significantly, by comparing the new structure with the conventional binary bit parallel one, it has been shown that the new structure is faster and requires a smaller area