A Low-Complexity Viterbi Decoder for Space-Time Trellis Codes

Author

Shr, Kai-Ting ; Chen, Hong-Du ; Huang, Yuan-Hao

Author_Institution

Dept. of Electr. Eng., Nat. Tsing-Hua Univ., Hsinchu, Taiwan

Volume

57

Issue

4

fYear

2010

fDate

4/1/2010 12:00:00 AM

Firstpage

873

Lastpage

885

Abstract

Space-time trellis code (STTC) has been widely applied to coded multiple-input multiple-output (MIMO) systems because of its gains in coding and diversity; however, its great decoding complexity makes it less promising in chip realization compared to the space-time block code (STBC). The complexity of STTC decoding lies in the branch metric calculation in the Viterbi algorithm and increases significantly along with the number of antennas and the modulation order. Consequently, a low-complexity algorithm to mitigate the computational burden is proposed. The results show that more than 70%, 78%, and 83% of the computational complexity is reduced for 2 ?? 2, 3 ?? 3, and 4 ?? 4 MIMO configurations, respectively. Based on the proposed algorithm, a reconfigurable MISO STTC Viterbi decoder is designed and implemented using 0.18 ??m 1P6M CMOS technology. The decoder achieves 11.14 Mbps, 8.36 Mbps, and 5.75 Mbps for 4-PSK, 8-PSK, and 16-QAM modulations, respectively.

Keywords

CMOS integrated circuits; MIMO communication; Viterbi decoding; antenna arrays; block codes; computational complexity; phase shift keying; space-time codes; trellis codes; 16-QAM modulations; 1P6M CMOS technology; 4-PSK modulation; 8-PSK modulation; MIMO systems; coded multiple-input multiple-output systems; computational complexity; low-complexity Viterbi decoder; reconfigurable MISO STTC Viterbi decoder; size 0.18 mum; space-time block code; space-time trellis codes; Branch metrics; MIMO; Viterbi decoder; space-time trellis code;

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2009.2027648

Filename

5357411