Title :
Modeling of stochastic BTI in small area devices and its impact on SRAM performance
Author :
Naphade, T. ; Mahapatra, Santanu
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol. Bombay, Mumbai, India
Abstract :
A comprehensive framework is developed to simulate device-level variability due to process variations and Bias Temperature Instability (BTI), and study the impact on circuits such as the SRAM cell. Stochastic simulation approach consisting of the stochastic Reaction Diffusion (RD) model for interface trap generation and stochastic two energy well model for charging of pre-existing bulk traps along with either simple exponential impact assumption or complete 3D TCAD simulation, is used to generate threshold voltage and threshold voltage shift distributions. A compact model approach to generate the threshold voltage distributions from the mean compact model through a procedure that exploits experimental relationship between mean and variance of threshold voltage shift distribution is described. The impact of device-level variability on the 6T-SRAM cell read and write operations is investigated.
Keywords :
SRAM chips; interface states; stochastic processes; technology CAD (electronics); 3D TCAD simulation; 6T-SRAM cell read and write operation; RD model; bias temperature instability; device-level variability simulation; interface trap generation; pre-existing bulk trap charging; simple exponential impact assumption; small area device; stochastic BTl modeling; stochastic reaction diffusion model; threshold voltage generation; threshold voltage shift distribution; Computational modeling; Integrated circuit modeling; Performance evaluation; Silicon; NBTI; SPICE; SRAM; TCAD; compact model; stochastic BTI; trap generation; trapping; variability;
Conference_Titel :
Microelectronics Technology and Devices (SBMicro), 2014 29th Symposium on
Conference_Location :
Aracaju
DOI :
10.1109/SBMicro.2014.6940078