Study of gate contact over active area

Author

Carmona, Mikael ; Hubert, Q. ; Lopez, L. ; Julien, F. ; Ogier, J.-L. ; Goguenheim, D. ; Beauvisage, L.

Author_Institution

STMicroelectron. - Rousset, Rousset, France

fYear

2014

fDate

1-5 Sept. 2014

Firstpage

1

Lastpage

4

Abstract

In this paper, analog and digital low-voltage MOSFETs having the gate contact over Shallow Trench Isolation (reference layout) or over active area (innovative layout) are studied. Using electrical parameters measurements, Linear Ramp Voltage Stress and Hot Carrier Injection stress, we demonstrate that moving the gate contact over active area does not degrade the performances and reliability of studied devices whatever the device area or oxide thickness (down to 2.1nm), and hence, could be a relevant solution in order to reduce the CMOS device area.

Keywords

MOSFET; hot carriers; reference circuits; active area; analog low-voltage MOSFET; device area; digital low-voltage MOSFET; electrical parameters measurements; gate contact; hot carrier injection stress; innovative layout; layout; linear ramp voltage stress; oxide thickness; reference layout; shallow trench isolation; Integrated circuit reliability; Logic gates; MOSFET circuits; Silicon; Transistors; Design optimization; performances; reliability;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics Technology and Devices (SBMicro), 2014 29th Symposium on

Conference_Location

Aracaju

Type

conf

DOI

10.1109/SBMicro.2014.6940082

Filename

6940082