DocumentCode :
1362145
Title :
Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume
Author :
Pei, Songwei ; Li, Huawei ; Li, Xiaowei
Author_Institution :
State Key Lab. of Comput. Archit., Tsinghua Univ., Beijing, China
Volume :
20
Issue :
12
fYear :
2012
Firstpage :
2157
Lastpage :
2169
Abstract :
We propose a flip-flop selection method to reduce the overall volume of transition delay test data, by replacing a small number of selected regular scan cells with enhanced scan cells. Relative measures are presented to reflect the gains when controlling a scan cell to a certain value, and guide the scan cell selection. Experimental results on larger IWLS 2005 benchmark circuits show that, to achieve the same fault coverage of the pure launch on capture (LOC) approach, the volume of test data can be reduced to a half on average by replacing only 1% of regular scan cells to enhanced scan cells. The transition delay fault coverage can also be improved using the proposed method with equally low area overhead.
Keywords :
delay circuits; flip-flops; integrated circuit testing; IWLS 2005 benchmark circuits; enhanced scan cells; fault coverage; flip-flop selection; partial enhanced scan; scan cell selection; selected regular scan cells; transition delay test data; transition test data volume; Benchmark testing; Circuit faults; Controllability; Flip-flops; Integrated circuit modeling; Testing; Fault coverage; flip-flop selection; launch on capture (LOC); partial enhanced scan; test data volume reduction;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2011.2170227
Filename :
6060943
Link To Document :
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