Drain induced barrier thinning on TFETs with different source/drain engineering

The goal of this work is to study the effect of high drain voltage bias on short channel devices of tunnel field effect transistors (TFETs). This work will analyze the drain induced barrier thinning (DIBT) calculated for devices with different source and drain engineering, varying characteristics such as channel length, junction doping abruptness and drain/channel junction gate underlap. The first part of this work explained the phenomenon based on Energy Band Diagrams and revealed the effect on transfer characteristic curves. In the second part, the DIBT has been chosen as a relevant parameter, since it includes the threshold voltage susceptibility to the bias conditions, which is important for both analog and digital applications. Finally, plotting DIBT for each parameter variation, it was noticed that devices with Gaussian doping profile and lower drain/channel junction gate underlap tend to present better results in terms of DIBT. The suitability of TFETs has been discussed based on these results.