Title :
A 32 nm, 3.1 Billion Transistor, 12 Wide Issue Itanium® Processor for Mission-Critical Servers
Author :
Riedlinger, Reid ; Arnold, Ron ; Biro, Larry ; Bowhill, Bill ; Crop, Jason ; Duda, Kevin ; Fetzer, Eric S. ; Franza, Olivier ; Grutkowski, Tom ; Little, Casey ; Morganti, Charles ; Moyer, Gary ; Munch, Ashley ; Nagarajan, Mahalingam ; Parks, Cheolmin ; Po
Author_Institution :
Intel Corp., Fort Collins, CO, USA
Abstract :
An Itanium® processor implemented in 32 nm CMOS with nine layers of Cu contains 3.1 billion transistors. The die measures 18.2 mm by 29.9 mm. The processor has eight multi-threaded cores, a ring based system interface and combined cache on the die is 50 MB. High-speed links allow for peak processor-to-processor bandwidth of up to 128 GB/s and memory bandwidth of up to 45 GB/s.
Keywords :
CMOS integrated circuits; cache storage; microprocessor chips; multi-threading; CMOS; Itanium processor; cache; memory bandwidth; mission-critical server; multithreaded cores; ring based system interface; size 32 nm; transistor; Arrays; Clocks; Iron; Microprocessors; Radio frequency; Registers; Architectural memory ordering; First level instruction (FLI); Intel scalable memory interconnect (SMI); Itanium processor family; double error correction, triple error detection (DECTED); failure in thousands (FIT); first level data (FLD); home agent; instruction buffer logic (IBL); instruction level parrallelism (ILP); integer execution unit (IEU); last level cache (LLC); memory controller (MC); mid level data cache (MLD); mid level instruction cache (MLI); ordering CZQueue (OZQ); quick path interconnect (QPI); random logic synthesized and placed circuitry (RLS); regional clock buffer (RCB); register file (RF); second level data TLB (DTB); single error correction, double error detection (SECDEC); small signal arrays (SSA); structured datapath (SDP); thermal design power (TDP); translation look-aside buffer (TLB);
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2011.2167809
