8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

Author

Kang, Uksong ; Chung, Hoe-Ju ; Heo, Seongmoo ; Park, Duk-Ha ; Lee, Hoon ; Kim, Jin Ho ; Ahn, Soon-Hong ; Cha, Soo-Ho ; Ahn, Jaesung ; Kwon, DukMin ; Lee, Jae-Wook ; Joo, Han-Sung ; Kim, Woo-Seop ; Jang, Dong Hyeon ; Kim, Nam Seog ; Choi, Jung-Hwan ; Chung

Author_Institution

Samsung Electron., Hwasung, South Korea

Volume

45

Issue

1

fYear

2010

Firstpage

111

Lastpage

119

Abstract

An 8 Gb 4-stack 3-D DDR3 DRAM with through-Si-via is presented which overcomes the limits of conventional modules. A master-slave architecture is proposed which decreases the standby and active power by 50 and 25%, respectively. It also increases the I/O speed to > 1600 Mb/s for 4 rank/module and 2 module/channel case since the master isolates all chip I/O loadings from the channel. Statistical analysis shows that the proposed TSV check and repair scheme can increase the assembly yield up to 98%. By providing extra VDD/VSS edge pads, power noise is reduced to < 100 mV even if all 4 ranks are refreshed every clock cycle consecutively.

Keywords

DRAM chips; statistical analysis; 8 Gb 3D DDR3 DRAM; TSV check; VDD/VSS edge pads; master-slave architecture; power noise; repair scheme; statistical analysis; storage capacity 8 Gbit; through-silicon-via technology; Assembly; CMOS logic circuits; CMOS technology; Integrated circuit interconnections; Master-slave; Noise reduction; Random access memory; Statistical analysis; Sun; Through-silicon vias; 3-D architecture; DDR3 DRAM; Through-silicon-via (TSV); assembly yield; connectivity check and repair; double data rate; gapless read; master; module; power edge pads; power noise reduction; rank; refresh; seamless; slave; stack; three dimensional; via first; via last; via middle;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2009.2034408

Filename

5357550