DocumentCode
1362824
Title
2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking
Author
Saito, Mitsuko ; Sugimori, Yasufumi ; Kohama, Yoshinori ; Yoshida, Yoichi ; Miura, Noriyuki ; Ishikuro, Hiroki ; Sakurai, Takayasu ; Kuroda, Tadahiro
Author_Institution
Dept. of Electron. & Electr. Eng., Keio Univ., Yokohama, Japan
Volume
45
Issue
1
fYear
2010
Firstpage
134
Lastpage
141
Abstract
An inductive-coupling programmable bus for NAND flash memory access in solid state drive (SSD) is presented. Compared to the conventional SSD, this wireless interface using relayed transmission reduces power consumption to 1/2, I/O circuit-layout area to 1/40, and achieves a data rate of 2 Gb/s in 0.18 ¿m CMOS process. In addition, since this wireless interface enables one package to contain 64 chips, the number of packages is reduced to 1/8.
Keywords
CMOS integrated circuits; NAND circuits; flash memories; CMOS; NAND flash memory stacking; bit rate 2 Gbit/s; inductive-coupling programmable bus; relayed transmission; size 0.18 mum; solid state drive; wireless interface; Bonding; Coupling circuits; Energy consumption; Interference; Packaging; Relays; Repeaters; Solid state circuits; Stacking; Wires; Chip to chip; SiP; inductive coupling; memory stacking; three-dimensional; wireless interconnect;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.2009.2034431
Filename
5357556
Link To Document