A 0.6 V Low-Power Wide-Range Delay-Locked Loop in 0.18 $\mu$ m CMOS

In this letter, a delay-locked loop (DLL) suitable for low-power and low-voltage operations is presented. To overcome the performance limitations, such as a restricted locking range and elevated output jitters, a novel voltage-controlled delay cell and a phase/frequency detector with a start controller are employed in the proposed DLL. Using a standard 0.18 mum CMOS process, the fabricated circuit exhibits a locking range from 85 to 550 MHz. The measured peak-to-peak and rms jitters at 550 MHz are 25.6 and 3.8 ps, respectively. Operated at a supply voltage of 0.6 V, the power consumption of the DLL circuit varies from 2.4 to 4.2 mW within the entire locking range.