On the equivalence of cost functions in the design of circuits by cost-table

In the cost-table approach to logic design, a function is realized as a combination of functions from a table. The objective of the synthesis is to find the least-cost realization, where realization cost is the sum of the costs of the functions used plus the cost of combining them. The costs of cost-table functions are defined by a cost function which represents chip area, speed, power dissipation, or a combination of these factors. It is shown that there is an arbitrarily large set S of cost functions which yield the same cost-table. This implies, for example, that every minimal realization of any function over a cost function in S is independent of the actual cost function used. With any cost function, if the cost of combining functions from a cost-table F is sufficiently large, the realizations behave as if the cost function belonged to S. That is, any minimal realization of a function f, using cost-table F, is one of the minimal realizations of f using F and a cost function in S. The interpretation of these results is that there are not as many distinct cost-tables as originally thought