• DocumentCode
    1363970
  • Title

    Spanning the product life cycle: RASSP DFT

  • Author

    Sedmak, Richard M. ; Evans, John S.

  • Author_Institution
    Self-Test Sevices, Amblers, PA, USA
  • Volume
    13
  • Issue
    3
  • fYear
    1996
  • Firstpage
    32
  • Lastpage
    42
  • Abstract
    This article describes a design for testability process for the RASSP program that is highly automated and hierarchical and also spans the entire life cycle. It features a new construct, the test strategy diagram for managing the test process
  • Keywords
    design for testability; digital signal processing chips; life testing; logic design; RASSP program; design for testability; design for testability process; life cycle; product life cycle; test strategy diagram; Built-in self-test; Circuit faults; Circuit testing; Control systems; Current measurement; Design for testability; Feedback; Libraries; Life testing; System testing;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.536094
  • Filename
    536094
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1363970