Implementation of digital HDTV video decoder by multiple multimedia video processors

Author

Lee, Charng L. ; Ho, Cheng S. ; Tsai, Shwu-Fang ; Wu, Ching-Fu ; Cheng, Jui-Ying ; Li-wei Wang ; Wang, Cornad ; Hu, Yi-Kwang ; Hou, Tsun-Jen ; Lee, Micro

Author_Institution

Comput. & Commun. Res. Labs., Ind. Technol. Tes. Inst., Hsinchu, China

Volume

42

Issue

3

fYear

1996

fDate

8/1/1996 12:00:00 AM

Firstpage

395

Lastpage

401

Abstract

A digital HDTV video decoder system is designed and implemented by using multiple multimedia video processors in a loosely-coupled multi-processor architecture. This decoder system can decompress video bitstream up to 20 Mbits/s and produce analog output at HDTV pixel rate. This design has the advantage of hardware scalability to adapt different picture resolutions and computation requirements. The design target is the video subsystem of a digital HDTV receiver

Keywords

decoding; digital signal processing chips; digital television; image resolution; multimedia communication; multiprocessing systems; parallel architectures; television receivers; video coding; 20 Mbit/s; HDTV pixel rate; analog output; decoder system; digital HDTV receiver; digital HDTV video decoder; hardware scalability; loosely coupled multiprocessor architecture; multiple multimedia video processors; picture computation requirements; picture resolutions; video bitstream decompression; video subsystem; Computer architecture; Decoding; Digital TV; Engines; HDTV; Hardware; Multimedia systems; Satellite broadcasting; Transform coding; Video compression;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.536136

Filename

536136