Experimental and Theoretical Analyses of the Electrical SOA of Rugged p-Channel LDMOS

Author

Podgaynaya, Alevtina ; Rudolf, Ralf ; Pogany, Dionyz ; Gornik, Erich ; Stecher, Matthias

Author_Institution

Infineon Technol. AG, Neubiberg, Germany

Volume

31

Issue

12

fYear

2010

Firstpage

1440

Lastpage

1442

Abstract

Numerical TCAD and transmission line pulse analysis of an electrical safe operating area of a robust p-channel lateral DMOS transistor is performed. The observed independence of the trigger current on the applied gate-source voltage is attributed to a lack of quasi-saturation effect which is usually observed in an n-channel LDMOS. The dependence of the trigger voltage on the length of channel and drift regions is also analyzed, and the tradeoff with the specific on-resistance (R_DSon) is given.

Keywords

MOS integrated circuits; electric breakdown; semiconductor epitaxial layers; technology CAD (electronics); electrical SOA; electrical safe operating area; numerical TCAD; p-channel lateral DMOS transistor; rugged p-channel LDMOS; transmission line pulse analysis; trigger current; Bipolar transistors; Conductivity; Current measurement; Electrostatic discharge; Logic gates; Modulation; Transistors; Electrical safe operating area (e-SOA); p-channel lateral DMOS (p-LDMOS); transmission line pulse (TLP);

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2010.2081337

Filename

5613913