DocumentCode :
1365611
Title :
An Ultra-Low-Power 24 GHz Low-Noise Amplifier Using 0.13 
CMOS Technology
Author :
Cho, Wei-Han ; Hsu, Shawn S H
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Volume :
20
Issue :
12
fYear :
2010
Firstpage :
681
Lastpage :
683
Abstract :
This study presents an ultra-low-power 24 GHz low-noise amplifier (LNA) using 0.13 μm CMOS technology. We propose of using the minimum noise measure (MMIN) as the guideline to determine the optimal bias and geometry of the transistors in the circuit. The power-constrained simultaneous noise and input matching (PCSNIM) technique is also employed for this design. With the proposed design approach, the LNA achieves a peak gain of 9.2 dB and a minimum NF of 3.7 dB under a supply voltage of 1 V. The associated power consumption is only 2.78 mW.
Keywords :
CMOS analogue integrated circuits; MMIC amplifiers; field effect MMIC; integrated circuit design; low noise amplifiers; low-power electronics; CMOS technology; LNA; PCSNIM technique; design approach; frequency 24 GHz; gain 9.2 dB; noise figure 3.7 dB; power 2.78 mW; size 0.13 mum; transistor bias; transistor geometry; ultralow-power low-noise amplifier; voltage 1 V; CMOS integrated circuits; Circuit topology; Low-noise amplifiers; Wireless communication; CMOS; k-band; low power; low-noise amplifier (LNA);
fLanguage :
English
Journal_Title :
Microwave and Wireless Components Letters, IEEE
Publisher :
ieee
ISSN :
1531-1309
Type :
jour
DOI :
10.1109/LMWC.2010.2085038
Filename :
5613950
Link To Document :
