DocumentCode
1365839
Title
Settling optimised sample-and-hold circuit with high-linearity input switch in 65 nm CMOS
Author
Shu, Guanghua ; Luo, Lei ; Shu, Chester ; Fan, Maoyu ; Ye, Feng ; Ren, Jinchang ; Xu, Jie ; Li, Ning
Author_Institution
Dept. of Microelectron. & Solid State Electron., Fudan Univ., Shanghai, China
Volume
46
Issue
22
fYear
2010
Firstpage
1485
Lastpage
1486
Abstract
A settling optimised sample-and-hold (SH) circuit with a wideband high-linearity input switch is presented. A proposed input switch with floating-well isolation achieves low on-resistance and high-linearity through a wide input frequency range. A method for the SH to acquire the optimised settling behaviour by choosing a feedback switch with suitable on-resistance is proposed to achieve low-power target. Simulation results show that the performance of the SH is improved considerably.
Keywords
CMOS analogue integrated circuits; sample and hold circuits; CMOS; floating-well isolation; optimised sample-and-hold circuit; size 65 nm; wideband high-linearity input switch;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el.2010.8724
Filename
5614004
Link To Document