• DocumentCode
    1365863
  • Title

    Junctionless 6T SRAM cell

  • Author

    Kranti, Abhinav ; Lee, Chia-Wei ; Ferain, I. ; Yan, Rong ; Akhavan, N. ; Razavi, P. ; Yu, Rong ; Armstrong, G.A. ; Colinge, J.-P.

  • Author_Institution
    Tyndall Nat. Inst., Univ. Coll. Cork, Cork, Ireland
  • Volume
    46
  • Issue
    22
  • fYear
    2010
  • Firstpage
    1491
  • Lastpage
    1493
  • Abstract
    The design of a 6T SRAM cell with 20 nm junctionless (JL) MOSFETs is reported. It is shown that a 6T SRAM cell designed with JL MOSFETs achieves a high static noise margin (SNM) of 185 mV, retention noise or hold margin (RNM) of 381 mV and writability current (IWR) of 33 A along with a low leakage current (ILEAK) of 2 pA at a supply voltage (VDD) of 0.9 V for cell and pull-up ratios of 1. Results offer a new opportunity to design future SRAM cells with nanoscale JL MOSFETs.
  • Keywords
    MOSFET circuits; SRAM chips; network synthesis; 6T SRAM cell; current 2 pA; current 33 muA; design; hold margin; junctionless MOSFET; retention noise; size 20 nm; static noise margin; voltage 0.9 V; voltage 185 mV; voltage 381 mV;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el.2010.2736
  • Filename
    5614008
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1365863