• DocumentCode
    1366279
  • Title

    Issue logic for a 600-MHz out-of-order execution microprocessor

  • Author

    Farrell, James A. ; Fischer, Timothy C.

  • Author_Institution
    Digital Equipment Corp., Hudson, MA, USA
  • Volume
    33
  • Issue
    5
  • fYear
    1998
  • fDate
    5/1/1998 12:00:00 AM
  • Firstpage
    707
  • Lastpage
    712
  • Abstract
    The logic and circuits are presented for a 20-entry instruction queue which scoreboards 80 registers and issues four instructions per cycle in a 600-MHz microprocessor. The request logic and arbiter circuits that control integer execution are described in addition to a novel compaction scheme that maintains temporal order in the queue. The issue logic data path is implemented in 141000 transistors, occupying 10 mm2 in a 0.35-μm CMOS process
  • Keywords
    CMOS digital integrated circuits; microprocessor chips; 0.35 micron; 600 MHz; CMOS process; arbiter circuits; compaction scheme; instruction queue; integer execution; issue logic; logic data path; out-of-order execution microprocessor; request logic; temporal order; CMOS logic circuits; CMOS process; Compaction; Decoding; Delay; Logic circuits; Microprocessors; Out of order; Registers; Wiring;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/4.668985
  • Filename
    668985
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1366279