Title :
A charge-transfer amplifier and an encoded-bus architecture for low-power SRAM´s
Author :
Kawashima, Shoichiro ; Mori, Toshihiko ; Sasagawa, Ryuhei ; Hamaminato, Makoto ; Wakayama, Shigetoshi ; Sukegawa, Kazuo ; Fukushi, Isao
Author_Institution :
Fujitsu Labs. Ltd., Kawasaki, Japan
fDate :
5/1/1998 12:00:00 AM
Abstract :
This paper proposes and reports a low-power SRAM using a charge-transfer (CT) pre-sense amplifier and a bus signal encoding scheme. The CT amplifier overcomes the Vth relative difference between the pair MOS transistors, and thus reduces the input offset voltage. The encoded-bus scheme reduces the number of signals being switched to cut the capacitive load. These read-path dynamic circuits have eight-timings which a low-power DLL produces. The fabricated 0.35-μm-rule 2k-by-16-bit SRAM operated at 50 MHz with the power dissipation of 5 mW at 1 V
Keywords :
CMOS memory circuits; SRAM chips; amplifiers; encoding; memory architecture; system buses; 0.35 micron; 1 V; 16 bit; 2 kbit; 5 mW; 50 MHz; DLL; capacitive load; charge-transfer pre-sense amplifier; encoded-bus architecture; low-power SRAM; offset voltage; pair MOS transistors; read-path dynamic circuit; CMOS technology; Circuits; Delay; Digital signal processing; Latches; MOS devices; MOSFETs; Operational amplifiers; Pulse amplifiers; Random access memory;
Journal_Title :
Solid-State Circuits, IEEE Journal of
