Title :
A reduced clock-swing flip-flop (RCSFF) for 63% power reduction
Author :
Kawaguchi, Hiroshi ; Sakurai, Takayasu
Author_Institution :
Inst. of Ind. Sci., Tokyo Univ., Japan
fDate :
5/1/1998 12:00:00 AM
Abstract :
A reduced clock-swing flip-flop (RCSFF) is proposed, which is composed of a reduced swing clock driver and a special flip-flop which embodies the leakage current cutoff mechanism. The RCSFF can reduce the clock system power of a VLSI down to one-third compared to the conventional flip-flop. This power improvement is achieved through the reduced clock swing down to 1 V. The area and the delay of the RCSFF can also be reduced by a factor of about 20% compared to the conventional flip-flop. The RCSFF can also reduce the RC delay of a long RC interconnect to one-half
Keywords :
CMOS logic circuits; VLSI; delays; flip-flops; leakage currents; timing; 1 V; RC delay reduction; VLSI; clock driver; leakage current cutoff mechanism; power reduction; reduced clock-swing flip-flop; Capacitance; Clocks; Delay; Energy consumption; Flip-flops; Integrated circuit interconnections; Logic; Power distribution; Very large scale integration; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
