• DocumentCode
    1366646
  • Title

    New insights into fully-depleted SOI transistor response after total-dose irradiation

  • Author

    Schwank, J.R. ; Shaneyfelt, M.R. ; Dodd, P.E. ; Burns, J.A. ; Keast, C.L. ; Wyatt, P.W.

  • Author_Institution
    Sandia Nat. Labs., Albuquerque, NM, USA
  • Volume
    47
  • Issue
    3
  • fYear
    2000
  • fDate
    6/1/2000 12:00:00 AM
  • Firstpage
    604
  • Lastpage
    612
  • Abstract
    In this work we explore the effects of total-dose ionizing irradiation on fully-depleted SOI transistors. Closed-geometry and standard transistors fabricated in two fully-depleted processes were irradiated with 10 keV X-rays. Our results show that increases in radiation-induced leakage current are caused by positive charge trapping in the buried oxide inverting the back-channel interface. At moderate levels of trapped charge, the back-channel interface is slightly inverted causing a small leakage current to flow. This leakage current may be amplified to considerably higher levels by impact ionization. At high levels of trapped charge, the back-channel interface is fully inverted and the gate bias has little effect on leakage current. Large increases in leakage currents can be obtained with or without impact ionization occurring in the channel region. For these transistors, the worst-case bias configuration was determined to be the “ON” bias configuration for both the cases where radiation-induced transistor response was dominated by charge buildup in the buried oxide and in the trench sidewall isolation. These results have important implications on hardness assurance
  • Keywords
    MOSFET; X-ray effects; impact ionisation; leakage currents; radiation hardening (electronics); silicon-on-insulator; 10 keV; SOI transistor response; Si; X-rays; back-channel interface inversion; buried oxide; charge buildup; closed-geometry transistors; fully-depleted SOI transistor; gate bias; hardness assurance; high trapped charge levels; impact ionization; ionizing irradiation; on bias configuration; positive charge trapping; radiation-induced leakage current; standard transistors; total-dose irradiation; trench sidewall isolation; worst-case bias configuration; Circuit testing; Electric variables; Geometry; Impact ionization; Isolation technology; Laboratories; Leakage current; Silicon on insulator technology; Single event upset; Space technology;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/23.856487
  • Filename
    856487