High Power-Supply-Rejection (PSR) Current-Mode Low-Dropout (LDO) Regulator

Author

Patel, Amit P. ; Rincón-Mora, Gabriel A.

Volume

57

Issue

11

fYear

2010

Firstpage

868

Lastpage

873

Abstract

Modern system-on-a-chip (SoC) solutions suffer from limited on-chip capacitance, which means that the switching events of functionally dense ICs induce considerable noise in the supplies. This ripple worsens the accuracy of sensitive analog electronics, such as ADCs, PLLs, and VCOs, etc. Without dropping a substantial voltage, point-of-load (PoL) low-dropout (LDO) regulators reduce (filter) this noise but only as much as their loop gains and bandwidths allow. This brief presents a 5-mA 1.5-μm bipolar current-mode LDO regulator that, with a higher bandwidth current loop, suppresses higher frequency noise by 49 dB (i.e., power-supply rejection) up to 10 MHz with only 68 nF at the output, which is 20 dB better than its voltage-mode counterpart.

Keywords

current-mode circuits; system-on-chip; voltage regulators; ADC; IC; LDO regulator; PLL; PSR; SoC; VCO; bandwidth current loop; bipolar current-mode LDO regulator; capacitance 68 nF; current 5 mA; current-mode low-dropout regulator; high power-supply-rejection; higher frequency noise suppression; on-chip capacitance; point-of-load low-dropout regulators; sensitive analog electronics; size 1.5 mum; substantial voltage drop; switching events; system-on-a-chip; Bandwidth; Gain; Impedance; Noise; Poles and zeros; Regulators; Switches; Current mode; dual loops; low-dropout (LDO) regulator; power-supply rejection (PSR); supply noise ripple;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2010.2068110

Filename

5617259