Title :
A modified TRAM architecture
Author :
Rai, S. ; Kirpalani, V.P.
Author_Institution :
Dept. of Electr. & Comput. Eng., Louisiana State Univ., Baton Rouge, LA, USA
fDate :
8/1/1996 12:00:00 AM
Abstract :
This paper modifies the tree RAM (TRAM) architecture (Jarwala and Pradhan, 1988) of multimegabit dynamic random access memories using a tree-star (TS) interconnection topology. The modified TS-RAM design offers a reduced access time and an improved yield for the proposed TS-RAM architecture. We also propose an improved built-in self test (BIST) approach for the architecture
Keywords :
built-in self test; memory architecture; multiprocessor interconnection networks; parallel architectures; random-access storage; TRAM architecture; built-in self test; interconnection topology; multimegabit dynamic random access memories; tree RAM; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Decoding; Integrated circuit interconnections; Random access memory; Read-write memory; Switches; Topology;
Journal_Title :
Computers, IEEE Transactions on
