DocumentCode
1366931
Title
Design and performances of a compensated mean-timer
Author
Dzahini, D. ; Pouxe, J. ; Rossetto, O.
Author_Institution
Inst. des Sci. Nucl., Univ. Joseph Fourier, Grenoble, France
Volume
47
Issue
3
fYear
2000
fDate
6/1/2000 12:00:00 AM
Firstpage
839
Lastpage
843
Abstract
An integrated mean-timer has been designed. This circuit integrates a compensation system in order to minimize thermal drift and process variations. This circuit designed in BiCMOS 0.8 μm integrates input and output ECL translators. The drift cancellation system is based on a regulated delay line controlled by a PLL. The PLL circuit can be disconnected and an external control voltage can be used. The circuit can also run without any cancellation system. In the last part, a sub-delay resolution system is discussed
Keywords
BiCMOS digital integrated circuits; delay lines; digital phase locked loops; nuclear electronics; 0.8 mum; BiCMOS; ECL translators; PLL circuit; compensated mean-timer; drift cancellation system; external control voltage; process variations; regulated delay line; sub-delay resolution system; thermal drift; BiCMOS integrated circuits; Control systems; Delay lines; Detectors; Inverters; Phase locked loops; Photomultipliers; Physics; Timing; Voltage control;
fLanguage
English
Journal_Title
Nuclear Science, IEEE Transactions on
Publisher
ieee
ISSN
0018-9499
Type
jour
DOI
10.1109/23.856527
Filename
856527
Link To Document