A novel dead-time compensation strategy of three-level inverter

Author

Guo Jing ; Gong Xuegeng ; Zhao Feng ; Wen Xuhui

Author_Institution

Key Lab. of Power Electron. & Electr. Drive, Inst. of Electr. Eng., Beijing, China

fYear

2014

fDate

Aug. 31 2014-Sept. 3 2014

Firstpage

1

Lastpage

5

Abstract

It is necessary to insert a switching delay time in pulse width modulation(PWM) voltage-fed inverters to avoid the short through of phase bridge. This causes well known dead time effect which distorts the output voltage and current. This paper puts forward a new three-level dead-time compensation method, which compensates dead time, turn on and off delay and forward voltage drop. A three-level inverter hardware platform was built based on FPGA and DSP, and the relevant experiment has been done on the 30kW three-phase induction motor. Experimental results verified the feasibility and correctness of the algorithm.

Keywords

PWM invertors; digital signal processing chips; field programmable gate arrays; induction motors; switching convertors; DSP; FPGA; PWM voltage-fed inverters; dead time effect; dead-time compensation strategy; field programmable gate arrays; phase bridge; pulse width modulation; switching delay time; three-level dead-time compensation method; three-level inverter; three-phase induction motor; Delays; Equations; Insulated gate bipolar transistors; Inverters; Mathematical model; Stators; Time-frequency analysis; dead-time compensation; forward voltage drop; three-level;

fLanguage

English

Publisher

ieee

Conference_Titel

Transportation Electrification Asia-Pacific (ITEC Asia-Pacific), 2014 IEEE Conference and Expo

Conference_Location

Beijing

Print_ISBN

978-1-4799-4240-4

Type

conf

DOI

10.1109/ITEC-AP.2014.6940985

Filename

6940985