System architecture and hardware design of the CDF XFT online track processor

Author

Holm, Sverre ; Freeman, J. ; Klein, Reinhard ; Lewis, J.D. ; Shaw, T.M. ; Ciobanu, Catalin

Author_Institution

Fermi Nat. Accel. Lab., Batavia, IL

Volume

47

Issue

3

fYear

2000

fDate

6/1/2000 12:00:00 AM

Firstpage

895

Lastpage

902

Abstract

A trigger track processor is being designed for CDF Run 2. This processor identifies high momentum (P_T>1.5 GeV/c) charged tracks in the new central outer tracking chamber for the CDF II detector. The design of the track processor, called the eXtremely Fast Tracker (XFT), is highly parallel and handle an input rate of 183 Gbits/sec and output rate of 44 Gbits/sec. The XFT is pipelined and reports the results for a new event every 132 ns. The XFT uses three stages, hit classification, segment finding, and segment linking. The pattern recognition algorithms for the three stages are implemented in Programmable Logic Devices (PLDs) which allow for in-situ modification of the algorithm at any time. The PLDs reside on three different types of modules. Prototypes of each of these modules have been designed and built, and are working. An overview of the hardware design and the system architecture are presented

Keywords

nuclear electronics; programmable logic devices; trigger circuits; CDF XFT online track processor; Extremely Fast Tracker; central outer tracking chamber; hardware design; hit classification; in-situ modification; pattern recognition algorithms; programmable logic devices; segment finding; segment linking; system architecture; trigger track processor; Cables; Detectors; Electrons; Hardware; Joining processes; Laboratories; Physics; Process design; Programmable logic devices; Prototypes;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.856714

Filename

856714