• DocumentCode
    1367673
  • Title

    Interval diagrams for efficient symbolic verification of process networks

  • Author

    Strehl, Karsten ; Thiele, Lothar

  • Author_Institution
    Lab. of Comput. Eng. & Networks, Swiss Fed. Inst. of Technol., Zurich, Switzerland
  • Volume
    19
  • Issue
    8
  • fYear
    2000
  • fDate
    8/1/2000 12:00:00 AM
  • Firstpage
    939
  • Lastpage
    956
  • Abstract
    In this paper, a representation of multivalued functions called interval decision diagrams (IDDs) is introduced. It is related to similar representations such as binary decision diagrams. Compared to other functional representations with regard to symbolic formal verification approaches, IDDs show some important properties that enable us to verify process networks and related models of computation more adequately than with conventional approaches. Therefore, a new form of transition relation representation called interval mapping diagram (IMD) is introduced. A novel approach to symbolic model checking of process networks is presented. Several drawbacks of traditional strategies are avoided using IDDs and IMDs. The resulting transition relation IMD is very compact, enabling fast image computations. Furthermore, no artificial limitations concerning buffer capacities or equivalent have to be introduced. Additionally, applications concerning scheduling of process networks are feasible. IDDs and IMDs are defined, their properties are described, and computation methods and techniques are given
  • Keywords
    Boolean functions; decision diagrams; formal verification; multivalued logic; scheduling; symbol manipulation; buffer capacities; computation methods; image computations; interval decision diagrams; multivalued functions; process networks; scheduling; symbolic model checking; symbolic verification; transition relation representation; Application software; Boolean functions; Computational modeling; Computer industry; Computer networks; Data structures; Formal verification; Job shop scheduling; Network synthesis; Processor scheduling;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.856979
  • Filename
    856979