Advanced technologies for optimized sub-quarter-micrometer SOI CMOS devices

Author

Hsiao, Tommy C. ; Liu, Ping ; Woo, Jason C S

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

Volume

45

Issue

5

fYear

1998

fDate

5/1/1998 12:00:00 AM

Firstpage

1092

Lastpage

1098

Abstract

Two manufacturable technologies of fully-depleted (FD) thin-film silicon-on-insulator (SOI) MOSFET´s for low-power applications are proposed in this paper. To maintain high current drive while aggressively thinning down the SOI film, silicide is to be formed on Ge-damaged silicon layers. Ge preamorphization facilitates silicide formation at low temperature (~450°C) and effectively controls the silicide depth without void formation. It also reduces the floating body effect. In addition, a reliable gate work-function engineering is introduced for good threshold voltage management. A p⁺SiGe/Si stack gate alleviates the threshold voltage instability of SOI due to film thickness nonuniformity and broadens the design window for channel doping. These advanced technologies, compatible with existing bulk CMOS technology, are integrated into SOI CMOS process. Excellent electrical device results are presented

Keywords

MOSFET; silicon-on-insulator; 0.25 micron; 450 C; Ge preamorphization; SOI film thinning; SiGe-Si; channel doping; current drive; floating body effect; fully-depleted thin-film SOI MOSFET; gate work function engineering; low-power electronics; manufacturable technology; p⁺SiGe/Si stack gate; silicide formation; sub-quarter-micrometer SOI CMOS device; threshold voltage; CMOS process; CMOS technology; Maintenance; Pulp manufacturing; Semiconductor films; Semiconductor thin films; Silicides; Silicon on insulator technology; Temperature control; Threshold voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.669541

Filename

669541