• DocumentCode
    1367976
  • Title

    High-current small-parasitic-capacitance MOSFET on a poly-Si interlayered (PSI:Ψ) SOI wafer

  • Author

    Horiuchi, Masatada ; Teshima, Tatsuya ; Tokumasu, Kazuya ; Yamaguchi, Ken

  • Author_Institution
    Central Res. Lab., Hitachi Ltd., Tokyo, Japan
  • Volume
    45
  • Issue
    5
  • fYear
    1998
  • fDate
    5/1/1998 12:00:00 AM
  • Firstpage
    1111
  • Lastpage
    1115
  • Abstract
    A new type of silicon-on insulator (SOI) structure has been fabricated by using direct bonding technology to bury multilayered films consisting of poly-Si and SiO2. A device with an ideal epitaxial channel structure was fabricated using a conventional MOS process on this novel multilayered SOI (100-nm SOI/10-nm SiO2/poly-Si/500-nm SiO2) wafer. In this device, the highly concentrated p+ poly-Si just beneath the nMOS channel region acts as a punchthrough stopper, and the buried thin backgate oxide under the SOI layer acts as an impurity diffusion barrier, keeping the impurity concentration in the SOI film at its original low level. The device fabricated was an ultrathin SOI MOSFET capable of operating at a current 1.5 times that of conventional hundred-nm devices at low voltages
  • Keywords
    MOSFET; buried layers; silicon-on-insulator; wafer bonding; MOS process; PSI wafer; buried thin backgate oxide; direct bonding; epitaxial channel structure; impurity concentration; impurity diffusion barrier; multilayered film; parasitic capacitance; polysilicon interlayered SOI wafer; punchthrough stopper; ultrathin SOI MOSFET; Amorphous materials; Immune system; Impurities; Insulation; MOSFET circuits; Rough surfaces; Semiconductor films; Silicon on insulator technology; Surface roughness; Wafer bonding;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.669551
  • Filename
    669551