An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution

Author

Chen, James C. ; Sylvester, Dennis ; Hu, Chenming

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

11

Issue

2

fYear

1998

fDate

5/1/1998 12:00:00 AM

Firstpage

204

Lastpage

210

Abstract

A simple, accurate method of measuring interconnect capacitances is presented. The test structure has excellent resolution, needs only DC measurements, and is compact enough for scribe-line implementation. These qualities make it suitable for measurement-based, interconnect capacitance characterization in a comparable fashion to current characterization efforts for MOSFET devices. The entire characterization scheme is demonstrated for a production 0.5 μm, three-level metal technology. The method not only provides an accurate assessment of actual capacitance variation but provides valuable feedback on the variability of physical parameters such as interlevel dielectric (ILD) thickness and drawn width reductions for process control as well

Keywords

capacitance measurement; integrated circuit interconnections; integrated circuit measurement; integrated circuit testing; 0.5 micron; DC measurements; capacitance variation; drawn width reductions; interconnect capacitance characterization; interlevel dielectric thickness; on-chip characterization method; process control; scribe-line implementation; sub-femto-farad resolution; test structure; three-level metal technology; Capacitance measurement; Circuit testing; Current measurement; Dielectric measurements; Frequency conversion; Integrated circuit interconnections; Integrated circuit technology; MOSFET circuits; Monitoring; Production;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/66.670160

Filename

670160