Title :
Dead-time compensation and realization method for 3-level NPC Inverter
Author :
Seok-Jin Hong ; Soo-Cheol Shin ; Hak-Sung Kim ; Chung-Yuen Won
Author_Institution :
Sungkyunkwan Univ., Suwon, South Korea
fDate :
Aug. 31 2014-Sept. 3 2014
Abstract :
3-Level Neutral Point Clamped (NPC) Inverter has 4 switches in each leg. 2 pairs of switches of the inverter operate complimentarily, S1 and S3 is a pair, the other is S2 and S4. But short circuit fault can be occurred due to a time distinction of turning on/off the switch. Thus, short circuit fault can be prevented by giving dead-time when turning on the switches which complementarily operate mutually. But these dead-time occur error between reference voltage and output voltage of each leg, and distort 3-phase output voltage and current. In this paper, a compensation method and its simple realizing method are proposed to minimize effect from these dead-time. The proposed method is implemented on software and does not require an additional hardware. The proposed method is applied to 3-Level NPC inverter and verified its validity through simulation.
Keywords :
clamps; compensation; invertors; power system faults; power system reliability; short-circuit currents; switches; switching convertors; 3-level NPC inverter; 3-level neutral point clamped inverter; current distortion realization method; output voltage distortion; reference voltage dead time compensation method; short circuit fault prevention; switch turning time distinction; Insulated gate bipolar transistors; Inverters; Space vector pulse width modulation; Switches; Turning; 3-Level NPC Inverter; Compensation; Compensation Method; Dead-time; Deadtime Compensation;
Conference_Titel :
Transportation Electrification Asia-Pacific (ITEC Asia-Pacific), 2014 IEEE Conference and Expo
Conference_Location :
Beijing
Print_ISBN :
978-1-4799-4240-4
DOI :
10.1109/ITEC-AP.2014.6941172