Title :
Dynamic clamp for pull-in time reduction
Author_Institution :
Dept. of Electron. Eng., Cenidet, Cuernavaca Morelos, Mexico
fDate :
10/1/1996 12:00:00 AM
Abstract :
A dynamic clamp aimed at reducing the pull-in time of a digital phase-locked-loop circuit being fed by intermittent signals is presented. This clamp is useful when the phase-locked loop (PLL) is used as a frequency multiplier, and is based on the assumption that the input signal frequency will not change significantly during the period of disconnection. Details on the additional circuitry required to achieve this goal are given, and experimental results are included
Keywords :
circuit feedback; digital phase locked loops; frequency multipliers; transient response; voltage-controlled oscillators; PLL; VCO; digital phase-locked-loop circuit; disconnection; dynamic clamp; frequency multiplier; intermittent signals; phase-locked loop; pull-in time reduction; signal frequency; transient response; Active filters; Circuits; Clamps; Frequency conversion; Frequency synchronization; Phase detection; Phase frequency detector; Phase locked loops; Sampling methods; Voltage-controlled oscillators;
Journal_Title :
Instrumentation and Measurement, IEEE Transactions on
