Technology mapping onto very-high-speed standard CMOS hardware

This paper addresses technology mapping onto very-high-speed (>500 MHz) standard CMOS hardware. Both the technology mapping concept implemented in PRIMUS 2 and the hardware, on which the tool has to rely, are presented and discussed in the paper. PRIMUS 2 maps any multioutput multilevel combinational Boolean equation onto a predefined and precharacterized cell library. The exceptionally high clock rate and, hence, the strict gate delay requirement calls for a new mapping concept; PRIMUS 2 maps the set of equations onto a pipeline comprising dynamic gate cells with very low logic complexity. The only user-defined constraint on the mapping is the clock rate, and depending on this clock rate, PRIMUS 2 maps onto an adequate set of cells with adequate constraints on the placement and routing. To be able to control the timing behavior, the gate cells have to be very regular in size and shape, the transistor sizes have to be fixed and the cell library must contain not only gate cells but also gate interconnect (wire) cells. Thus, the maximal clock rate of the resulting hardware can be accurately tuned and controlled. A 1 GHz 1.0-μm double-metal single-poly cell library has been designed and simulated in order to demonstrate the feasibility of the PRIMUS 2 technology mapping concept