DocumentCode :
1369528
Title :
Globally optimal floorplanning for a layout problem
Author :
Moh, Teng-Sheng ; Chang, Tsu-Shuan ; Hakimi, S. Louis
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
Volume :
43
Issue :
9
fYear :
1996
fDate :
9/1/1996 12:00:00 AM
Firstpage :
713
Lastpage :
720
Abstract :
In this paper, the floorplanning problem for a layout problem is formulated as a global optimization problem. The area of each building block is assumed to be fixed. However, its width and height are allowed to vary subject to aspect ratio constraints. Also, a block may be arbitrarily oriented in parallel to the xy orthogonal axes, subject to partition constraints with associated adjacency relationships. The objective is to minimize the rectangular area of the entire layout. By formulating the problem appropriately, it becomes a geometric programming problem. Its global minimum can then be found by using standard convex optimization techniques. The problem formulation and its conversion to a convex optimization problem are first illustrated through a simple example. The general procedure is then described and the effectiveness of the approach demonstrated through numerical examples
Keywords :
VLSI; circuit layout CAD; circuit optimisation; geometric programming; integrated circuit layout; minimisation; adjacency relationships; aspect ratio constraints; convex optimization techniques; geometric programming problem; global optimization problem; globally optimal floorplanning; partition constraints; rectangular area minimisation; Circuit synthesis; Hardware; Logic design; Pins; Process design; Routing; Shape; Very large scale integration; Wires; Wiring;
fLanguage :
English
Journal_Title :
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on
Publisher :
ieee
ISSN :
1057-7122
Type :
jour
DOI :
10.1109/81.536741
Filename :
536741
Link To Document :
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