DocumentCode :
1369798
Title :
Fabrication Cost Analysis and Cost-Aware Design Space Exploration for 3-D ICs
Author :
Dong, Xiangyu ; Zhao, Jishen ; Xie, Yuan
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
Volume :
29
Issue :
12
fYear :
2010
Firstpage :
1959
Lastpage :
1972
Abstract :
3-D integration technology is emerging as an attractive alternative to increase the transistor count for future chips. The majority of the existing 3-D integrated circuit (IC) research is focused on the performance, power, density, and heterogeneous integration benefits offered by 3-D integration. All such advantages, however, ultimately have to translate into cost evaluation when a design strategy has to be decided. Consequently, system-level cost analysis at early design stages is imperative to decide on whether 3-D integration should be adopted. This paper presents a cost estimation method for 3-D ICs at early design stages and proposes a set of cost models that include wafer cost, 3-D bonding cost, package cost, and cooling cost. The proposed 3-D IC cost estimation method can help designers analyze the cost implication for 3-D ICs during the design space exploration at the early stage, and it enables a cost-driven 3-D IC design flow that can guide the design choice toward a cost-effective direction. Based on the proposed cost estimation method, this paper demonstrates two case studies that explore the cost benefits of 3-D integration for application-specific integrated circuit designs and many-core microprocessor designs style, respectively. Finally, this paper suggests the optimum partitioning strategy for future 3-D IC designs.
Keywords :
application specific integrated circuits; cooling; costing; integrated circuit bonding; integrated circuit design; integrated circuit packaging; microprocessor chips; 3D bonding cost; 3D integrated circuit; application-specific integrated circuit designs; cooling cost; cost estimation; cost-aware design space exploration; fabrication cost analysis; heterogeneous integration; many-core microprocessor designs; package cost; partitioning strategy; system-level cost analysis; transistor count; Bonding; Fabrication; Guidelines; Integrated circuit modeling; Microprocessors; Power demand; Solid modeling; 3-D integration; application-specific integrated circuit (ASIC); cost; microprocessor;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2010.2062811
Filename :
5621044
Link To Document :
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