Cutting the high cost of testing

A modeling approach to the overly long testing of analog and mixed-signal devices that saves substantially on time and cost is described. The discussion focuses on the particular case of a 13 bit analog-to-digital converter (ADC). The problems that arise in testing ADCs are identified, showing that the success of the test method depends critically on the quality of the model. Two types of models are examined, physical-sensitivity-based models and empirical-learning-based models, and it is noted that the latter are especially attractive for performance-testing applications like the ADC example. An 18-parameter model of the 13 bit ADC was developed using a combination of physical and empirical modeling techniques and was highly successful. With an array process to speed up the computations, the computational overhead can be kept below 1 s per device, so the test time, which is reduced by a factor of 128, becomes negligible.<>