• DocumentCode
    1370024
  • Title

    Integrated Systems [systems on a chip]

  • Author

    Bartelink, Dirk J.

  • Author_Institution
    Hewlett-Packard Co. Labs., Palo Alto, CA, USA
  • Volume
    43
  • Issue
    10
  • fYear
    1996
  • fDate
    10/1/1996 12:00:00 AM
  • Firstpage
    1678
  • Lastpage
    1687
  • Abstract
    Integrated Systems are defined as batch-fabricated interconnections of complex digital integrated circuits with analog interface circuits and transducers, such as sensors. By providing the cost, performance and reliability levels of monolithic integration, they offer potential advantages over multi-chip modules assembled with packaging technology. This paper studies the required process technology, as well as design, test and packaging issues, for integrating wide varieties of systems. The goal is to delineate the necessary steps in bringing Integrated Systems to market within a realistic period. With monolithic integration as the ultimate aim, a multi-chip entry point is identified that can start system technology on a learning curve of cost reduction using the same scaling principles that drive integrated circuits. Three challenges to be surmounted are identified in streamlining the I/O´s and progressing along a learning curve, namely I/O scaling, I/O loading, and full-functional test. The “composite IC” is the entry point. A large chip, containing only global interconnects and power distribution, acts as a silicon backplane. Subsystem-chips, such as digital microprocessors or sensors, are flip-chip mounted using the accuracy of MEMS processing to fabricate “snap-together” physical and electrical interfaces with high reproducibility. While similar to conventional MCM´s, this chip-to-chip connection has few compromises over on-chip connections. By keeping the fabrication responsibility within one organization, just as in monolithic chips, there is no need for incoming inspection. Added ESD protection and test-head loading are avoided on interior nodes by a new intra-factory method of testing
  • Keywords
    analogue integrated circuits; digital integrated circuits; flip-chip devices; integrated circuit design; integrated circuit interconnections; integrated circuit packaging; integrated circuit technology; integrated circuit testing; microassembling; Integrated Systems; Si; Si backplane; analog interface circuits; batch-fabricated interconnections; chip-to-chip connection; complex digital integrated circuits; flip-chip mounting; full-functional testing; global interconnects; monolithic integration; packaging; power distribution; process technology; scaling principles; sensors; transducers; Circuit testing; Costs; Digital integrated circuits; Integrated circuit interconnections; Integrated circuit packaging; Integrated circuit reliability; Integrated circuit technology; Monolithic integrated circuits; Sensor systems; Transducers;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.536814
  • Filename
    536814