Functional fault simulation as a guide for biased-random test pattern generation

An approach to the generation of test patterns for implementation-level faults is presented. The approach involves fault simulation on a functional-level description of a combinational VLSI design, together with an appropriate functional fault model. The methodology uses the difference fault model (DFM), a formal abstraction of the faults at the implementation level, as the basis for fault simulation at the functional level. Incremental information from fault simulation results provides guidance for the generation of nonuniformly random test patterns using a backtracing process. The quality of the generated patterns is measured in terms of their coverage of implementation faults