Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor

Author

Dighe, S. ; Vangal, S.R. ; Aseron, P. ; Kumar, S. ; Jacob, T. ; Bowman, K.A. ; Howard, J. ; Tschanz, J. ; Erraguntla, V. ; Borkar, N. ; De, V.K. ; Borkar, S.

Author_Institution

Intel Labs., Intel Corp., Hillsboro, OR, USA

Volume

46

Issue

1

fYear

2011

Firstpage

184

Lastpage

193

Abstract

In this paper, we present measured within-die core-to-core Fmax and leakage variation data for an 80-core processor in 65 nm CMOS and 1) populate a parameterized energy/performance model to determine the most energy-efficient operating point for a workload; 2) examine impacts of per-core clock and power gating on optimal dynamic voltage-frequency-core scaling (DVFCS) operating points; and 3) compare improvements in energy efficiency achievable by variation-aware DVFCS and core mapping on Single-Voltage/Multiple-Frequency (SVMF), Multiple-Voltage/Single-Frequency (MVSF) and Multiple-Voltage/Multiple-Frequency (MVMF) designs. Variation-aware DVFS with optimal core mapping is shown to improve energy efficiency 6%-35% across a range of compute/communication activity workloads. A new dynamic thread hopping scheme boosts performance by 5%-10% or energy efficiency by 20%-60%.

Keywords

CMOS integrated circuits; microprocessor chips; multiprocessing systems; power aware computing; 80-core teraFLOPS processor; CMOS; core-to-core Fmax; dynamic voltage frequency scaling; optimal core allocation; thread hopping; within die variation; Clocks; Multiprocessors; Power measurement; Resource management; Temperature measurement; Voltage measurement; 80-core; Core-to-core variations; DVFS; TeraFLOPS processor; dynamic voltage frequency scaling; network-on-chip (NoC); variation-aware; within-die variations;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2010.2080550

Filename

5621842