DocumentCode
1370205
Title
Optimal VLSI sorting with reduced number of processors
Author
Alnuweiri, Hussein M. ; Kumar, V. K Prasanna
Author_Institution
Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
Volume
40
Issue
1
fYear
1991
fDate
1/1/1991 12:00:00 AM
Firstpage
105
Lastpage
110
Abstract
A new parallel architecture is presented which has p processors and N =n 2 memory locations, each consisting of 2s bits. The proposed organization can sort N s -bit numbers, where s =O ((1+ε) log N ), ε>0, in time t =O (N log N ÷p ), for p in the range 1 to √N log √N . This result is optimal in the sense that the product of the number of processors and the parallel sorting time is equal to the sequential complexity of sorting. Also, the constant factors involved in the algorithm complexity are relatively small. When p =√N log √N , the time required for sorting N numbers on the proposed organization is O (√N ), which is the same time required by a two-dimensional mesh array, a mesh of trees organization, or a pyramid computer, all with O (N ) processors, to sort N numbers
Keywords
VLSI; computational complexity; parallel architectures; sorting; algorithm complexity; optimal VLSI sorting; parallel architecture; parallel sorting time; pyramid computer; sequential complexity; trees organization; two-dimensional mesh array; Computer architecture; Computer networks; Costs; Hardware; Multiprocessor interconnection networks; Parallel algorithms; Parallel architectures; Proposals; Sorting; Very large scale integration;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.67326
Filename
67326
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