Novel test structure for the measurement of electrostatic discharge pulses [MOS ICs]

A test structure for the measurement of electrostatic discharge (ESD) pulses using a floating gate transistor is presented. It was found that ESD pulses of a wide range of magnitudes can cause a shift in the threshold voltage of such a floating gate transistor. The change in device characteristics was quantified by measuring the drain current. For a given geometry, the response was proportional to the magnitude of the ESD event for a particular range of voltages. This particular range of sensitivity also scales linearly with the capacitance ratio of the devices studied. Numerical simulation of a simple model of the device leads to sufficiently accurate results for the design of a specific sensitivity if the processing parameters are considered. The lowest sensitivity determined was 60 V