Title :
Using spatial information to analyze correlations between test structure data [semiconductor IC manufacture]
Author :
Kibarian, John K. ; Strojwas, Andrzej J.
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
fDate :
8/1/1991 12:00:00 AM
Abstract :
A modeling strategy is presented that captures the dependence of performance on the spatial position of the chips on the water. The information from this model can be used to determine whether the variance and correlation of parameters are due to either random variation or deterministic function of wafer position. The modeling strategy covers deterministic variations of the mean as a function of wafer position. The authors provide a method to determine the amount of correlation which is due to the common spatial dependence (referred to as spatial correlation). When coupled with knowledge about the manufacturing process, the diagnosis system can determine the physical reasons for the yield loss. The problem is formalized and a solution is developed. Extensions to this model are discussed
Keywords :
integrated circuit manufacture; integrated circuit testing; production testing; semiconductor device models; deterministic function; diagnosis system; manufacturing process; modeling strategy; random variation; semiconductor IC manufacture; spatial correlation; spatial position; test structure data; wafer position; yield loss; Circuit faults; Circuit testing; Covariance matrix; Fault diagnosis; Information analysis; Integrated circuit testing; Integrated circuit yield; Monitoring; Semiconductor device measurement; Semiconductor device testing;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
