An interconnect scheme for reducing the number of contact pads on process control chips

Author

Walton, Anthony J. ; Gammie, William ; Fallon, Martin ; Stevenson, J.T.M. ; Holwill, Robert J.

Author_Institution

Dept. of Electr. Eng., Edinburgh Univ., UK

Volume

4

Issue

3

fYear

1991

fDate

8/1/1991 12:00:00 AM

Firstpage

233

Lastpage

240

Abstract

An approach is presented to reduce the number of pads required by electrical test structures by using a multiplexed interconnect scheme. This passive multiplexed scheme requires only two levels of interconnect and can be used for transistors, electrical verniers, yield monitoring, reliability evaluations, continuity tests, and measuring the resistance of tracks. The basic measurement procedure to access individual components is to force a voltage on one of the access pads and then ground one of the group terminals via an ammeter. While an even number of pads is not mandatory it is recommended since this maximizes the efficiency of pad usage

Keywords

integrated circuit manufacture; integrated circuit testing; metallisation; multiplexing; production testing; contact pads reduction; continuity tests; electrical test structures; electrical verniers; interconnect scheme; measurement procedure; passive multiplexed scheme; process control chips; reliability evaluations; track resistance; transistors; yield monitoring; Ammeters; Atherosclerosis; Contacts; Electric variables measurement; Electrical resistance measurement; Force measurement; Monitoring; Process control; Resistors; Testing;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/66.85945

Filename

85945