C5M-a control-logic layout synthesis system for high-performance microprocessors

In high-end microprocessors, control-logic timing can gate the cycle time, but control logic is specified late and changes often. Custom design is too time consuming for control implementation, and application specific integrated circuit (ASIC)-like methods have difficulty achieving the required performance/area targets. In this paper, we describe C5M, a new layout system for high-performance control logic which has been successfully used in the design of a recent 400 MHz IBM processor. Results from this design are used to show that C5M achieves near custom quality with high productivity and predictability