Title :
Network-flow-based multiway partitioning with area and pin constraints
Author :
Liu, Huiqun ; Wong, D.F.
Author_Institution :
Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
fDate :
1/1/1998 12:00:00 AM
Abstract :
Network flow is an excellent approach to finding min-cuts because of the celebrated max-flow min-cut theorem. For a long time, however, it was perceived as computationally expensive and deemed impractical for circuit partitioning. Recently, the algorithm FBB successfully applied network flow to two-way balanced partitioning. It for the first time demonstrated that network flow was a viable approach to circuit partitioning. In this paper, we present FBB-MW, which is an extension of FBB, to solve the problem of multiway partitioning with area and pin constraints. Experimental results show that FBB-MW outperforms previous approaches for multiple field programmable gate array partitioning. In particular, although FBB-MW does not employ logic replication and logic resynthesis, it still outperforms some other algorithms, which allow replication and resynthesis for optimization
Keywords :
circuit layout CAD; circuit optimisation; field programmable gate arrays; integrated circuit layout; logic CAD; logic partitioning; FBB-MW algorithm; area constraints; circuit partitioning; field programmable gate array partitioning; min-cuts; multiple FPGA partitioning; network-flow-based multiway partitioning; pin constraints; two-way balanced partitioning; Clustering algorithms; Constraint theory; Design automation; Field programmable gate arrays; Integrated circuit interconnections; Integrated circuit synthesis; Logic devices; Partitioning algorithms; Pins; Programmable logic arrays;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on