A 160-MHz fourth-order double-sampled SC bandpass sigma-delta modulator

Author

Bazarjani, Seyfi ; Snelgrove, W. Martin

Author_Institution

Qualcomm. Inc., San Diego, CA, USA

Volume

45

Issue

5

fYear

1998

fDate

5/1/1998 12:00:00 AM

Firstpage

547

Lastpage

555

Abstract

A fully differential double-sampled switched-capacitor (SC) architecture for a fourth-order bandpass ΣΔ modulator is presented. This architecture is based on a double-sampled SC delay circuit. The effect of opamp nonidealities (finite dc gain and nonzero input capacitance) on the notch frequency of this modulator is analyzed. The modulator is implemented in a 0.5-μm CMOS technology and operates at a clock frequency of 80 MHz, making the effective sampling rate 160 MHz. The image signal is about 40 dB below the fundamental signal. The measured signal-to-noise-plus-distortion (SNDR) is 47 dB (not including the image) over a 1.25-MHz bandwidth centered at 40 MHz. The circuit operates at 3 V and consumes 65 mW

Keywords

CMOS integrated circuits; delay circuits; sampled data circuits; sigma-delta modulation; switched capacitor networks; 0.5 micron; 1.25 MHz; 160 MHz; 3 V; 65 mW; clock frequency; delay circuit; effective sampling rate; finite dc gain; fourth-order double-sampled SC bandpass circuit; image signal; nonzero input capacitance; opamp nonidealities; sigma-delta modulator; signal-to-noise-plus-distortion; CMOS technology; Capacitors; Circuit noise; Clocks; Delay; Delta-sigma modulation; Digital communication; Digital modulation; Frequency conversion; Image sampling;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.673636

Filename

673636